System for reducing the visibility of the noise in television pictures

ABSTRACT

A television signal noise reduction system employs a movement detector for automatically selecting one of three parallel processing paths, the first of which passes the video signal without modification and the other two of which calculate different weighted averages of the current pixel and surrounding pixels from the current frame and the previous frame.

This is a continuation of application Ser. No. 895,912, filed Apr. 13,1978, now abandoned.

The present invention relates to systems for reducing the visibility ofthe noise in television pictures using digital techniques.

Studies already exist on the reduction of noise in television picturesusing analog techniques, for example, those described in French Pat. No.2169830. However, these analog methods for the treatment of televisionsignals do not allow advantage to be taken of the spatial and temporalrelationships in a television picture in such a flexible manner as dodigital techniques.

Digital techniques were originally applied to complete televisionpictures for technical reasons concerned with transmission and wereintended to reduce the number of transmitting channels involving thepossibility of frame rate reduction. A technical article entitled"Combining intraframe and frame-to-frame coding for television" by J. O.Limb and others which appeared in the American technical review, theBell System Technical Journal of July-August 1974, can be referred to inthis regard. However, these previously proposed digital techniques werenot intended for the reduction of the visibility of noise in thepicture.

This problem of the reduction of the visibility of noise arisesparticularly when the noise originates from a source itself, forinstance when using old film in bad condition taken from archives, orwhere television recordings have been made in bad lighting conditionsetc. This problem can also arise in cases in which the televisionsignals are received under adverse conditions.

The invention is intended to minimize this problem of the visibility ofthe noise by applying digital techniques to a television signal.

More especially, the invention is intended for use in a systemincorporating an analog-digital converter, whose output is linked, onthe one hand, to the input of a digital coder circuit, and, on the otherhand, to the input of a movement detector circuit, whose output islinked to the command input of the digital coder circuit. The digitalcircuit output is linked to a digital analog converter input emittingthe television signal. The digital coder circuit incorporates a seriesof digital filter circuits of the applied digital signal. The selectionof the filter circuit, whose output is linked to that of the digitalcoder circuit, is controlled by the output signal from the movementdetector.

Another feature is the filter circuit incorporating a calculationcircuit, whose first input is linked to the coder circuit input andwhose second input is linked to the output of a delay line. The delay isequal to the duration of a complete picture. The output is connected onthe one hand to the filter circuit output and on the other hand to theinput of the delay line. The calculation circuit determines the weightedsum of the values applied to the two inputs.

According to another feature, the weighting coefficients of the valuesapplied to the two calculation circuit inputs are equivalent to 1/2.

Another feature is that the weighting coefficients of the values appliedrespectively to the first input and the second input of the calculationcircuit are equivalent to 1/4 and 3/4 respectively.

Another feature is that the weighting coefficients of the values appliedrespectively to the first input and the second input of the calculationcircuit are equivalent to 1 and 0 respectively.

Another feature is that the filter circuit outputs are connected by aselector controlled by the movement detector circuit and connect onlyone of the outputs at any one time to the digital coder output.

Another feature is that, instead of one delay line for each filtercircuit, one single delay line is provided whose input is connected tothe digital coder circuit output and whose output is amplified at thesecond inputs of the calculation circuits of the filter circuits.

Another feature is that the movement detector circuit incorporates anevaluation circuit whose first input is connected to the input of thedetector circuit, and whose second input is connected to the output of aframe memory, whose input is linked to the input of the detectorcircuit. The evaluation circuit incorporates a calculation facility inorder to obtain a series of digital variations, represented by absolutevalues, between the respective digital values of an initial series ofpoints comprising the point being currently processed and the pointsadjacent to the currently processed point in the same frame, and therespective values of the second state of points corresponding to thepoints in the first series in the preceding picture. There is a means ofcomparison of the individual digital variations with an initial digitalthreshold value. There is also an evaluation of the variations which aregreater than the first digital threshold value. A decision circuitcompares the result issued by the calculation facility with the secondset of threshold values and issues, depending on the result of thecomparison, a command signal for selection of the filter circuitoutputs.

According to a further feature, the movement detector circuitincorporates an evaluation circuit whose first input is connected to thedetector circuit input, and whose second input is connected to theoutput of a frame memory whose input is connected to the detectorcircuit input. The evaluation circuit has a calculating arrangement toprovide a series of digital variations between the respective digitalvalues of a first series of points comprising the point being currentlyprocessed and the neighboring adjacent points on the same line, and therespective digital values of a second series of points corresponding tothe points in the first series in the previous frame, thereby obtainingthe weighted value of said variations. The system makes a comparison ofthe absolute value of the sum issued by the calculation facility withthe threshold value. This calculation facility issues a command signalfor the selection of the filter circuit output.

The above mentioned features of the invention, in addition to otherfeatures, will be demonstrated more clearly with reference to thefollowing description of embodiments which is given by way of examplewith reference to the accompanying drawings, in which:

FIG. 1 is a block diagram showing a system for the reduction of visiblenoise in accordance with the invention.

FIG. 2 illustrates the respective positions of a point being currentlyprocessed, adjacent points in the same frame, adjacent points in thepreceding frame and points corresponding to the point being currentlyprocessed and to the adjacent points in the same frame in the precedingpicture.

FIG. 3 is a block diagram of a memory used in the system in FIG. 1.

FIG. 4 is the diagram of a first movement detector for use in the systemin FIG. 1.

FIG. 5 is the diagram of a second movement detector for use in thesystem in FIG. 1.

In FIG. 1 the system for reduction of visible noise disturbance in atelevision picture incorporates an input 1 for analog video signalsoriginating, for example, from a television camera and suppying ananalog digital converter 3, which receives from a source 3 sample timingsignals. The converter 2 supplies on the one hand a processor circuit 4and on the other hand a movement detector 5, whose output is connectedto the command input 6 of the processor circuit 4. The output of theprocessor circuit 4 is connected to the input of a digital-analogconverter 7, which supplies a processed signal user circuit for examplea television picture receiver 8.

The processor circuit 4 incorporates, in the example described, threeprocessor channels of which the first contains a delay circuit 9, thesecond a calculation circuit 10 and the third a calculation circuit 11.The second and third channels also include a common memory 12. The inputof circuit 9 is connected to the output of converter 2 while its outputis connected to the first input of an AND gate 13. The first input ofcircuit 10 is connected to the output of converter 2, while its outputis connected to the first input of AND gate 14. The first input ofcircuit 11 is connected to the output of converter 2 while its output isconnected to the first input of AND gate 15. The outputs of gates 13 to15 are connected respectively to the three inputs of an OR gate 16,whose output is connected on the one hand to the input of the convertor7, and on the other hand to the input of the memory 12, whose output isconnected, in parallel, to the second inputs of circuits 10 and 11.

The detector 5 incorporates a calculation and a decision circuit 17whose first input is connected to the output of converter 2, and amemory 18 whose input is also connected to the input of converter 2 andwhose output is connected to the second input of circuit 17. The circuit17 also incorporates a threshold regulator input 19. The outputs ofcircuit 17, which, in the example described are three in number and bearthe reference numbers 20 to 22, are connected respectively, via 6, tothe second inputs of gates 13 to 15.

The converter 2 is a standard circuit which samples the analog signalapplied by 1, with a sample frequency applied in 3 of 12 MHz, forexample, for a video signal band width of 6 MHz, and subsequentlyencodes the samples in a standard PCM code of eight binary element forinstance. Thus all the system connections between 2 and 7, with theexception of the link passing via 6, comprise eight lines fortransmission of the eight binary elements of each sample. It must beunderstood that if the input signal on line 1 is already digitized, theconverter 2 may be omitted.

Before describing the structure of the calculator circuits 10 and 11 andof the memory 12, we shall first consider, with reference to FIG. 2, thevarious types of digital processing possible. We shall assume only thatthe memory 12 allows access at any time to a certain number of samplescorresponding to points spatially and temporarily adjacent to a sampledpoint. In FIG. 2 we have shown, for the currently considered framecontaining the point E8 under consideration, the nine points E1, E2, E3,E7, E8, E9, E13, E14, E15 for the frame preceding the frame underconsideration, the six points SM'4, SM'5, SM'6, SM'10, SM'11, SM'12 andfor the preceding picture, the points SM1, SM2, SM3, SM7, SM8, SM9,SM13, SM14 and SM15, in addition to the processed point R8 underconsideration.

The points E7 and E9 are the points immediately adjacent to the currentpoint E8 on the same line. The points E1 to E3 are those in the sameframe on the line immediately above and are immediately above the pointsE7 to E9. The points E13 to E15 are beneath point E7 to E9 on the linebelow. The points SM'4 to SM'6 are on the line immediately above in thepreceding frame, while the points SM'10 to SM'12 are on the lineimmediately below. The points SM1, SM2 etc. correspond in the precedingpicture to the points E1, E2 etc. respectively.

It should be remembered that, as the values of the points mentioned inFIG. 2 are known, one can, by combining these values, provide for threetypes of filter; a spatial filter which only affects points E1 to E15contained in the same picture, a temporal filter which affects thecurrent point E8 and its corresponding point SM8 in the precedingpicture, or finally a spatio-temporal filter which affects the series ofpoints in FIG. 2. It should be noted that the spatial filterincorporates two interesting special features, which are the spatialhorizontal filter, affecting the points E7, E8 and E9 and the spatialvertical filter affecting the points E2, E8 and E14. A more complexhorizontal filter could affect a greater number of points on the sameline on either side of the current point E8. It should also be notedthat, in a temporal filter, the sampling times must coincide spatiallywhich means that the sampling structure must remain constant from onepicture to the next.

Finally the temporal filter may be simple when the value of the pointSM8 is that of the preceding picture received directly from the sourceor reiterated when this value is that which results from processing ofthe corresponding points of the preceding picture.

Practical experiments have shown that purely spatial filtering does notsubstantially reduce visible noise disturbance and in addition causesdegradation of the useful picture information so much so that in thiscontext spatial filtering has negative or zero value. On the other handtemporal filtering, and in particular reiterated temporal filtering,causes substantial reduction in visible noise disturbance withstationary pictures; however, temporal filtering causes easilyperceptible blurring effects in moving pictures.

For this reason, the invention provides for temporal filtering of thestationary points of each picture, but with use of a movement detectorit also provides for reduction, and where necessary for completeelimination, of temporal filtering of the points judged by the movementdetector to be moving.

Before describing the movement detector 5, used in this invention, anexample of picture memory will be described with reference to FIG. 3,which allows the values of the points mentioned in FIG. 2 to bedelivered at different output points. This memory is standard and isonly described in order to illustrate the invented system. Itincorporates a signal input 23 which supplies a first branch comprisingtwo delay lines RL1 and RL2, a second branch comprising two delay linesR1 and R2, and third branch consisting of a memory RT1 and an output E1.The part common to the lines RL1 and RL2 supplies a branch comprisingtwo lines R3 and R4 and the output E9. The output of the line RL2supplies the branch comprising two delay lines R5 and R6 and the outputE3. The part common to the lines R1 and R2 supplies the output E14 andthe free output of R2 supplies the output E13. The part common to thelines R3 and R4 supplies the output E8 and the free output of R4supplies the output E7. The part common to the lines R5 and R6 suppliesthe output E2 and the free output of R6 supplies the output E1.

The output of the memory RT1 supplies a first branch comprising a delayline RL3, a second branch comprising two delay lines R7 and R8, a thirdbranch comprising a delay line RT2 and the output SM'12. The output ofthe line RL3 supplies a branch comprising two delay lines R9 and R10 andthe output SM'6. The part common to the lines R7 and R8 supplies theoutput SM'11, and the free output of R8 supplies the output SM'10. Thepart common to the lines R9 and R10 supplies the output SM'5 and thefree output of R10 supplies the output SM'4. The output of the line RT2supplies the first branch comprising two delay lines RL4 and RL5 and asecond branch comprising two delay lines R11 and R12 and the outputSM15. The part common to the lines RL4 and RL5 supplies a first branchcomprising two delay lines R13 and R14 and the output SM9. The freeoutput of line RL5 supplies a branch comprising two delay lines R15 andR16 and the output SM3. The part common to the lines R11 and R12supplies the output SM14 and the free output of R12 supplies the outputSM13. The part common to lines R13 and R14 supplies the output SM8 andthe free output of R14 supplies the output SM7. The part common to linesR15 and R16 supplies the output SM2 and the free output of R16 suppliesthe output SM1.

It appears that in FIG. 3 the outputs E1, E2, . . . SM15 carry the samereferences as points E1 to SM15 in FIG. 2 for which they provide thecorresponding values. The delay lines RT1 and RT2 cause the signalsapplied to them to be delayed respectively for one frame, or in a 625line television system, for 20 ms. The delay lines RL1 to RL5 cause thesignals applied to them to be delayed for one line, or in the samesystem for 64 s. The delay lines R1 to R16 cause the signals applied tothem to be delayed respectively for a period dependant on the samplingfrequency used for digitization, that is for the number of points perline. In the example described this would involve a delay of 83.3 nscorresponding to a sampling frequency of 12 MHz with 624 points peractive line. Delay lines can be manufactured according to MOStechnology.

The practical structure of memories constituted by these delay lines maybe simplified when the process or processes to be applied to the signalshave been selected. Thus, as has been shown above, the processes whichseem most efficient for stationary pictures are reiterated temporalfilters of which the most simple only affect the current point E8 andthe point SM8 or RSM8, if one calls the point deduced from thecorresponding point processed in the preceding picture by passagethrough two consecutive frame memories, such as RT1 and RT2, RSM8.

In the example in FIG. 1, the delay line memory 12 thus comprises twoconsecutive frame memories which delay the processed signal transmittedto the output of the OR gate 16. The calculation circuit 10 performs thefollowing calculation:

    b=(E8+RSM8)×1/2

where E8 is the value of the current point originating from 2 and RSM8is the value issued by memory 12 and b is the value issued by calculator10.

The calculation circuit 11 performs the following calculation:

    c=(E8+3×RSM8)×1/4

where c is in this case the value issued by 11.

The delay 9 is intended to compensate for the delay caused by circuits10 and 11 so that the signal a which it transmits is applied to gate 13at the same time that b and c are applied respectively to AND gates 14and 15. It appears therefore, that movement detector circuit 5 allowsthe choice to be made as to which of the AND gates 13 to 15 is to beopened to allow the OR circuit 16 to transmit the correct processedsignal to the converter 7 and to the picture receiver 8 on the one hand,and on the other hand to the input of delay line memory 12 for use inthe processing of the following picture.

The operation of the movement detector 5 will now be described, firstlyin relation to a first example of the detector circuit 17, as shown inFIG. 4.

The circuit in FIG. 4 comprises an input connected to the outut ofconverter 2, which supplies the branch composed of two lines RL6 and RL7in series and the first input of a digital subtraction circuit S1. Thepart common to RL6 and RL7 is connected to the first input of a digitalsubtraction circuit S2. The free output of RL7 is connected to the firstinput of a digital subtraction circuit S3. It also incorporates an inputconnected to the output of memory 18 which supplies a branch comprisingtwo consecutive lines RL8 and RL9 and the second input of S1. The pointcommon to RL8 and RL9 is connected to the second input of S2 and thefree output of RL9 to the second input of S3. Lines RL6 to RL9 aresimilar to delay lines RL1 to RL5 in FIG. 3. The circuits S1 to S3 arestandard logic subtraction circuits. It appears that the values appliedto their inputs are those of adjacent points on the same vertical linein the current picture and the preceding picture.

The output of subtract circuit S1 is connected to the input of astandard logical circuit AV1 which only retains the absolute value ofthe algebraic difference issued by S1. The output of the circuit AV1 isconnected to the first input of a logical comparison circuit C1 whosesecond input is connected to the threshold value input 19 and whichissues a binary digit 1, if the value applied by AV1 is greater thanthat of the threshold applied at input 19, and a binary digit 0 in theopposite case. The logic output of the circuit C1 is connected on theone hand to the third input of an adder circuit ADD 1, and on the otherhand to the input of a delay line R17. The output of delay line R17 ison the one hand connected to the second input of the circuit ADD1, andon the other hand to the input of a delay line R18, whose output isconnected to the first input of the circuit ADD1.

The output of the circuit S2 is connected to the input of the circuitAV2, identical to AV1, followed by a circuit C2, identical to C1, whichis itself followed by two delay lines R19 and R20, assembled in the sameway as R17 and R18. The output of R20 is connected to the fourth inputof ADD1, the output of R19 to the fifth input and the output of C2 tothe sixth input. Similarly, the circuit S3 is followed by a circuit AV3,identical to AV1, then by a circuit C3 identical to C1, and by two delaylines R21 and R22. The output of delay line R22 is connected to the 7thinput of ADD1, the output of delay line R21 to the 8th input and theoutput of comparator C3 to the 9th input.

The output of the adder circuit ADD1 is connected at the input of acomparison circuit L1 incorporating two threshold value inputs M and N.The output of the circuit L1 is constituted by the three control lines20, 21 and 22, of which only one at a time is activated to open one onlyof the three AND gates 13 to 15. The line 20 is connected on the onehand to the input of a delay line R23, and on the other hand to theinput of a delay circuit constituted by two lines RT3 and RT4 in series.A switch contact 25 allows connection of the output of R23 or RT4 asrequired to the input 26 of the circuit L1.

It should be noted that the lines R17 to R23 have a delay of one pointin any one line, for example R1, and that the lines RT3 and RT4 have adelay of one frame like RT1.

As has been seen above, the circuits S1 to S3 process points situated onthe same vertical line in the current picture and in the precedingpicture in order to obtain three different samples in one vertical line.The lines R17 to R22, assembled in a similar way to the lines R1 to R6,allow simultaneous transmission of information to the respective inputsof the circuit ADD1, where threshold levels are passed during samplingof a current point E8, and of the eight points surrounding it as shownin FIG. 2, for which the relevant information is transmitted by R19.Therefore the circuit ADD1 allows calculation of the number of pointsout of the nine sampled whose amplitude has varied by a value greaterthan the threshold level in relation to the corresponding points in thepreceding picture. The circuit L1 is a logic circuit which activates oneof the lines 20 to 21 as shown in the following table of values:

    ______________________________________                                               x                                                                      y        x < M       M < x < N  x > N                                         ______________________________________                                        y = 0    22          21         20                                            y = 1    21          20         20                                            ______________________________________                                    

In this table x represents the number of points showing flexuremeasurements whose absolute values are greater than the threshold level19 and is transmitted by ADD1. The letter y represents a decision takenfor a preceding point and M and N represent the decision thresholdvalues chosen arbitrarily.

In practice, the preceding point on which y is based is, in relation tocurrent point E8, either the point immediately preceding it in the sameline, that is E7, when the switch 25 connects the output of R23 to theinput 26 of logic circuit L1, or a corresponding point of the precedingpicture, that is SM8, when the switch 25 connects the output of delayline RT4 to the input 26. The y value has the value 0 when, for thepreceding point, E7 or SM8, there have been few variations in the seriesof the nine points which surround it, which means that the line 22 hasbeen activated, and the value 1 in the other cases, that is when theline 20 has been activated.

When the preceding point considered is E7, one is said to be takingaccount of the spatial hysteresis. When the point SM 8 is underconsideration, one is said to be taking account of temporal hysteresisfrom one picture to the next.

In practice it is possible to regulate the values of the thresholds onwire the value of 19 of M and of N subjectively in order to obtain thepicture or rather the series of pictures which seems best. Experiencehas shown that the values of M and N can be fixed permanently, but thatit was interesting to be able to play with the value of the threshold of19 which may be at the disposal of an operator.

It is evident that one could not increase the thresholds M, N, etc. inthe circuit L1, by providing for more than three parallel filtercircuits in the processing circuit 4, in order to process the picturepoints by more progressive filtering. However, experience has shown thatprocessing by three circuits, such as those described above, allowed adistinct improvement.

FIG. 5 shows another example of the circuit 17 in FIG. 1. The circuit inFIG. 5 incorporates an input connected to the output of converter 2,which supplies the first input of a digital subtraction circuit S4 andan input connected to the output of memory 18 which supplies the secondinput of circuit S4. The output of S4 is connected to a delay circuitcontaining four delay lines R25 to R28 assembled consecutively. Theoutput of subtractor S4 is, in turn, connected to the first input of adigital adder circuit ADD2 via a digital divider DIV1. The point commonto delay lines R26 and R27, is connected via a digital divider DIV2, tothe second input of the adder circuit ADD2. The output of delay R28 isconnected to the third input of the circuit ADD2 via a digital dividerDIV3. The delay lines R25 to R28 are identical to delay line R1.

The output of circuit ADD2 is connected to the input of a standard logiccircuit AV4, which only retains the absolute value of the algebraiccalculation issued by ADD2. The output of the circuit AV4 is connectedto an input of a logical comparison circuit C4, whose second input isconnected to the threshold value input 19, and which activates eitherline 20 or 22 depending on whether the output value of AV4 is greater orless than the threshold value.

It should be noted that the division relationships between the circuitsDIV1, DIV2 and DIV3 should preferably be 1/4, 1/2 and 1/4 respectively.It appears that the values applied to the inputs of ADD2 correspond,given the above weighting, to the values of the points flanking thepoint E8 on the same line, but displaced by two steps. It is evidentthat one could provide for more than three inputs for the circuit ADD2and affect the points immediately adjacent to E8 on the same line bychanging the weighting coefficients. This can be achieved by connectingthe points common to delay lines R25 and R26, and delay lines R27 andR28 by dividers at the additional inputs of ADD2.

It should also be noted that the input of threshold value 19 is able toprovide two comparison threshold values which enables three outputlines, 20, 21, and 22, at the output of C4 to be used. It is alsopossible to provide for comparator C4 a complex circuit containing, forexample, the series of circuits L1, R23, RT3, RT4 and the switch 25 inFIG. 4, to cause spatial or temporal hysteresis.

In the examples described above, it has been assumed that the movementdetector output signals can only serve to select the filter circuitoutput to be used. However one could also provide for a calculationcircuit such as calculators 10 or 11, whose weighting coefficients ofthe addition to be carried out could be controlled by the movementdetector output signals. The series of filter circuits could thereforebe reduced to a single filter circuit, whose adding circuit would haveweighting coefficients dependent on the decision information provided bythe movement detector.

It is also evident from the above that the process performed in theprocess detector requires a certain length of time. For instance in thecircuit in FIG. 5, the second point following the point E8 on the sameline must be available before the comparator C4 is able to make adecision. To compensate for this delay, a delay line 27 between theoutput of the convertor 2 and the processor circuit 4 is provided for,which compensates for the delay in the movement detector 5.

The system according to the invention may be applied to colour pictureprocessing either by applying colour filters to the brightness only orto the picture components, on condition that the composite signal hasbeen processed beforehand so that it recurs from one picture to thenext.

Although the principles of the present invention have been describedabove in relation to particular usages, it must be understood that thedescription has only been given as an example and does not limit thescope of the invention.

We claim:
 1. A system for improving the signal-to-noise ratio in anincoming video signal, said system comprising first and second storagemeans for separately storing video signals for comparison with a laterreceived incoming video signal, transmitting means for directlytransmitting incoming video signals as they are received; first meansjointly responsive to said video signals stored in said first storagemeans and to said later received incoming video signals for respectivelydeveloping output video signals, movement detector means includingprocessing means responsive to said incoming video signal and toprevious incoming video signals stored in said second storage means fordeveloping multi-condition control signals and for utilizing internallydeveloped difference signals for indicating the differences between acurrent incoming video signal point and its neighboring video signalpoints and the corresponding points of video signals stored in saidsecond storage means, gating means responsive to said multi-conditioncontrol signals for selectively connecting either said incoming signalfrom said transmitting means or said output video signals from saidfirst means to an output terminal and also to said first storage means,means included in said movement detector responsive to said differencesignals relative to a predetermined threshold level for deliveringbinary signals to indicate whether said difference is above or belowsaid threshold level, and logic circuit means also included in saidmovement detector means responsive to said binary signals and to atleast one of said multi-condition control signals for providing saidmulti-condition control signals to said gating means.
 2. The system asin claim 1 wherein the first means comprises two-input adder means, theweighting coefficients of values applied to both inputs of the addermeans being equal to 1/2.
 3. The system as in claim 1 wherein theweighting coefficients of the values applied respectively to the firstand second inputs of the first means are equal respectively to 1/4 and3/4.
 4. The system of claim 1 and means for feeding back saidmulti-condition control signals to said logic circuit means according tothe following truth table:

    ______________________________________                                               x                                                                      y        x < M       M < x < N  x > N                                         ______________________________________                                        y = 0    22          21         20                                            y = 1    21          20         20                                            ______________________________________                                    

where: 20, 21, 22 represent three separate gating control signals; xrepresents the number of points exceeding the threshold level; yrepresents decisions for preceding points; and M and N are thresholdvalues.
 5. The system of claim 4 characterized in that said first meansincludes a plurality of filter circuits and said movement detector meansincludes at least one two-input evaluation circuit means having a firstinput connected to the input of the detector means and a second inputconnected to the output of said second storage means, the input of saidsecond storage means being connected to the input of the detector means,said evaluation circuit means incorporating means for providing a seriesof digital signals representing differences between the respectivedigital values of a first series of video signal points including thecurrent points being processed and points adjacent the current point andcorresponding points of the preceding picture taken from said secondstorage means; means for comparing the individual difference signals toa first digital threshold value; means responsive to said comparingmeans for providing said command signal for selecting the outputs ofsaid transmitting means and said filter circuits in accordance with theresults of the comparison.